IEEE

Improving LLM-Based Verilog Code Generation with Data Augmentation and RL

Abstract: Large language models (LLMs) have recently attracted significant attention for their potential in Verilog code generation. However, existing LLM-based methods face several challenges, ...
IEEE

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

Abstract: Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works have shown a ...
GitHub

A verilog implementation of UART Communication protocol

uart_project/ ├── rtl/ │ ├── uart_tx.v # UART Transmitter (FSM-based) │ ├── uart_rx.v # UART Receiver (FSM-based) │ ├── baud_gen.v # Baud rate generator (tick for bit sampling) │ └── uart_top.v # ...
GitHub

indhu2006/Verilog-Code-for-Swapping-Three-Numbers

To design and simulate a Verilog HDL code for swapping the values of three numbers without using any temporary variables, and verify the correctness of the swapping operation through a testbench using ...