Near-memory HBM for LLM inference; processing-in-memory for 3D DRAM; SDV hardware abstraction; 3nm GAAFET SRAM self-heating ...

High-volume products get more than their fair share of attention in the semiconductor world, but most chips don’t fit into that category. While a few huge fabs and offshore assembly and test (OSAT) ...

AI-driven compute demands have led to several distinct supply chain bottlenecks for data centers. Legacy power management ...

Scaling NoCs across chiplets requires earlier validation of coherency, congestion, thermal effects, and fault behavior.

Tools are currently built with a defined notion of how they will be used. For agentic solutions they will be transformed into collections of callable engines. Agents may be built by EDA companies for ...

Experts at the Table: Semiconductor Engineering sat down to discuss the opportunities and challenges of using AI in chip design, with Thomas Andersen, vice president for AI & Machine Learning at ...

Newer nonvolatile memory (NVM) technologies are poised to take over from flash in embedded applications on newer process ...

Photonics is forcing EDA to verify not just chips, but the physics of light inside full electro-optical systems.

Synopsys’ Dana Neustadter and Ilya Tolchinsky warn that physical AI creates a different kind of security challenge that requires continuous runtime assurance to ensure outputs remain within safe ...