Design-Reuse

Synopsys Launches SystemVerilog Catalyst Program

MOUNTAIN VIEW, Calif., October 6, 2003 - Synopsys, Inc. (Nasdaq: SNPS), the world leader in semiconductor design software, today announced its SystemVerilog Catalyst Program. The SystemVerilog ...
Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

Membership in the Questa Vanguard Program is open to those companies who work with Mentor Graphics verification customers and wish to promote the development and use of EDA tools, verification IP, ...
Design-Reuse

Denali Joins Synopsys SystemVerilog Catalyst Program

PALO ALTO, Calif. -- June 7, 2004-- Denali Software today announced that it has joined the Synopsys SystemVerilog Catalyst program. The industry program is designed to speed support of SystemVerilog ...
EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
Business Wire

IEEE Standards Association and Accellera Systems Initiative Team to Deliver Revised SystemVerilog Standard through IEEE Get Program

SAN JOSE, Calif.--(BUSINESS WIRE)--(at the 2013 Design and Verification Conference) -- Accellera Systems Initiative (Accellera) announce today they have once again partnered with the IEEE Standards ...
EDN

Open-source libraries boost SystemVerilog

SANTA CRUZ, Calif. — Setting up a SystemVerilog verification environment involves many steps, but verification consultant Mike Mintz promises to make it easier with two open-source verification ...