It’s no secret to anyone that chip design gets harder every year. There are two major trends driving these ever-increasing challenges. The first is the continual scaling down to smaller design nodes.

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

Apple executives recently talked about Apple Silicon in an interview, explaining the Neural Engine and the company's chip design process. Laura Metz, the Director of Product Marketing, Anand Shimpi of ...

When it comes to taking advantage of new silicon technology, design enablement teams must deliver accurate process design kits (PDKs) to mitigate the complexity of evolving semiconductor processes.

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it is collaborating with TSMC to enhance productivity and optimize product performance for AI-driven advanced-node designs and 3D-ICs.

DesignWare PVT monitoring and sensing subsystem IP supports cutting-edge technologies targeting AI, data center, HPC, consumer and 5G markets Innovative, modular architecture offers new sensor ...

AWS expands supplier relationship with Marvell for AI and data center connectivity products. Marvell expands relationship with AWS for electronic design automation (EDA) in the cloud to deliver its ...

TL;DR: Synopsys has successfully completed silicon bring-up of its LPDDR6 IP on TSMC's advanced N2P process, delivering up to 86GB/sec bandwidth and significant generational upgrades over LPDDR5. This ...

Leveraging Tower’s Mature Silicon Photonics Foundry Platform to Enable Scalable FMCW LiDAR. MIGDAL HAEMEK, Israel, and SAN JOSE, CA. – January 05, 2026 – Tower Semiconductor ...