EDN

Mentor provides concurrent HDL checking for FPGA and ASIC designers

Mentor Graphics released a new concurrent design checking and creation environment for FPGA and ASIC design teams working with Verilog, SystemVerilog, and VHDL design languages. The capability is ...
Semiconductor Engineering

HDL Simulation Acceleration Solution For Microchip FPGA Designs

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...
WatersTechnology

Impulse Announces C-to-HDL FPGA Compiler

Impulse Accelerated Technologies has announced the latest version of its C-to-HDL compiler, providing field-programmable gate array (FPGA) coding support for Arista Switch users. FPGAs, which are ...
EDN

Mentor improves HDL suite for ASIC, FPGA designs

SAN MATEO, Calif.—Mentor Graphics Corp. has enhanced its HDL Designer Series front-end design suite to provide better ways to create and manage hardware description languages in ASIC and FPGA designs.
Hackaday

Spade Language

Spade is an open-source hardware description language (HDL) developed at Linköping University, Sweden. Other HDLs you might have heard of include Verilog and VHDL. Hardware engineers use HDLs to ...